The present invention relates to data receivers, especially for high-speed wired communications.
High-speed serial data transmission is conventionally performed according to either a direct current (DC) coupled scheme or an alternating current (AC) coupled scheme, as shown in FIGS. 1 and 2, respectively. In a DC coupled scheme, as shown in FIG. 1, the transmitter is conductively connected to the receiver at DC as well as AC via a DC conducting medium, e.g., through one or more cards, cables, connectors, packages, and backplanes, etc. By contrast, as shown in FIG. 2, in an AC coupled scheme, AC coupling capacitors 7 are placed in the path of signals between the transmitter and remote receiver to allow only AC signals to pass, while blocking the flow of current at DC between the transmitter and receiver. For this reason, the AC coupling capacitor is also known as a DC blocking capacitor. DC blocking capacitors can be provided on the same integrated circuit, i.e., the “chip” which contains the transmitter or the receiver, or otherwise on the same package or in a discrete device provided off the chip. The values of DC blocking capacitors typically range between about 10 nF and about 100 nF.
The DC coupled scheme is used only when transmitter and receiver are designed to operate at the same or a similar common mode voltage level. FIG. 1 illustrates a serial data communication system including a transmitter 2, a receiver 3, and a pair of differential signal lines 4 and 5 which carry a pair of differential signals Dn and Dp representing a data bit signal between the transmitter 2 and the receiver 3. In such communication system, the common mode supply voltage Vtr to the receiver is set to the same level as the common mode supply voltage Vtt to the transmitter, to avoid DC current flow between the transmitter and the receiver.
In some DC coupled systems, the transmitter and receiver are designed to perform best when operated together as a matched pair, in which case the transmitter and receiver are said to be “compatible”. At minimum, DC coupling requires that the common mode level of the signal arriving at the receiver is within the range in which the receiver is designed to operate.
However, when the common mode level of the signal arriving at the receiver lies outside of the voltage range that the receiver is designed to handle, the receiver cannot amplify the signal efficiently. Poor data recovery then results. In such a case, or when the common mode level of the arriving signal is not known a priori, an AC coupled scheme is recommended, instead of a DC coupled scheme. With reference to FIG. 2, in an AC coupled communication system, the receiver independently sets the common mode level of the received signal to a predetermined desirable level. In AC coupled systems, this is accomplished through the use of a supply voltage (“Vtr”) at the receiver to supply a DC current for maintaining the common mode signal level, in a manner which is independent from the supply voltage Vtt used to maintain the common mode signal level at the transmitter. As also shown in FIG. 2, a termination resistor 8, having a value matching the impedance of the transmission line, e.g., 50 ohm, is placed between a supply voltage Vtr and the data input signals.
Although an AC coupled scheme is advantageous for filtering out low-frequency noise and relaxing common mode demand, it requires that the data signal be transmitted according to a DC balanced code. Stated another way, the data signal arriving at the receiver must have an equal number of bits having the value “1” as the number of bits having the value “0” bits within each sequentially transmitted block having a given number of data bits. This is needed in order to prevent the common mode voltage level of the signal from shifting. An AC coupled scheme also requires the data signal to transition frequently between “1”s and “0”s. In other words, the receiver cannot properly decode a signal in which a long consecutive string of “1s” or “0s” appears at the input to the receiver. Moreover, in systems in which only the data signal is transmitted but not the clock, it is difficult to recover the clock from the transmitted signal when the transmitted signal has long strings of either “1”s or “0”s. An “8b10b” code is an example of a DC balanced code. An 8b10b code guarantees that the data signal transitions at least twice for every 10 bits. However, the 8b10b code is not without drawbacks. A data signal transmitted via an 8b10b code requires 10 signal bits to transfer 8 bits of information, equivalent to 20% of bandwidth loss. For these reasons, it is desirable to avoid using an AC coupled transmission scheme except in situations in which the voltage supply levels used at the transmitting and receiving ends of a communication system are incompatible.
It would be desirable to provide a front end interface for a serial data communication receiver which can be utilized in multiple ways, in communication systems which are DC coupled as well as AC coupled, and in high-speed environments in which channel characteristics cannot be predicted a priori. Heretofore, such flexibility has not been available in SerDes communication systems.
FIG. 3 is a block diagram illustrating the architecture of a prior art receiver complex 10 which has a targeted data transmission rate of between 2.5 and 3.2 Gbs. The receiver complex 10 has a front end interface unit FEI 11 at the input end of the receiver 12, the FEI 11 providing line terminations for the differential signals Dn and Dp and circuitry for switching between modes for AC coupling and DC coupling. However, the FEI 11 provides only fixed termination impedances to the differential signal lines Dn and Dp arriving at the receiver 12 (and also to lines Dn′ and Dp′), making its design somewhat inflexible. The receiver complex 10 also includes a built-in-self-test (BIST) unit 16, which verifies operation upon initializing the receiver 12 by inputting a known test data pattern into the receiver 12 and then verifying the outcome. The BIST unit 16 raises an “ERROR” flag 19 when the receiver 12 does not correctly receive the test data pattern.
The receiver 12 includes a pre-amplifier 210, a sample latch 220, and 2:1 demultiplexer 230, also referred to herein as a “demux”. The pre-amplifier 210 amplifies the incoming signals using a peaking device to extend the bandwidth. A pair of latches is provided in the sample latch 220. Each takes a one-half rate clock signal (as compared to the recovered clock rate of the incoming data signal) from a clock and data recovery circuit CDR 18 and uses it to sample and latch alternate bits from the signal data stream output by the pre-amplifier. The demultiplexer 230 has two latches. Each of the latches in the demultiplexer 230 then uses a one-quarter rate clock signal to demultiplex the data and then feed the data into a shift register inside a decision feedback equalizer (DFE) 13. The DFE 13 operates as a deserializer as well as an adaptive equalizer. The DFE takes the amplified and latched data signal and outputs n bits of data in parallel to logic circuitry as Dout.
The DFE makes a decision as to the value of the present bit in a serial stream of bits (as signals Dn″ and Dp″) that appears at the receiving end of the channel. The DFE operates by weighting the voltage of the present bit with the values of the bits that come before the present bit and the bits that come after the present bit. As an adaptive equalizer, the coefficients used to weight the values of the bits are updated during operation of the DFE in response to changes that occur in the channel, as well as changes that occur in the degree of intersymbol interference. The prior art receiver complex 10 may be operated in conjunction with a transmitter having a feed forward equalizer (FFE), in which the tap coefficients cannot be adjusted by feedback based on the results of receiving operation by the DFE 13. Receiver complex 10 has no provision for transmitting information for updating FFE coefficients of the transmitter from the receiver complex 10 back to the transmitter.
In the receiver complex 10 shown in FIG. 3, the clock data recovery (CDR) unit 18 extracts the clock from the incoming data stream using a phase rotator and a clock recovery algorithm. Through output 21, the CDR over-samples the differential data signals at the output of the pre-amplifier 210 and a digital circuit detects the time position of an edge (signal transition) of the differential data signals. The CDR determines a desirable time position at which to sample the differential data signals. The clock signal 22 generated by the CDR is used to operate the DFE 13. Feedback 20 from the DFE assists the CDR in maintaining the edge of the generated clock signal at the correct position.
Ideally, a front-end interface unit should be adapted for use in both an AC coupled transmission scheme and a DC coupled scheme. FIG. 4 is a schematic diagram depicting a front-end interface circuit according to the prior art. In this prior art circuit, the pair of resistors Rup and Rdn are used to terminate the signals PADP and PADN, respectively. A power-down signal (PWDN) and a mode selecting signal (ACMODE) are used to set the receiving mode to either AC or DC coupling modes. DC coupled mode is selected when the control signals presented to the circuit have the values PWDN=0, and ACMODE=1. In DC coupled mode, transistor P11 is turned on, and transistors P12 and N12 are turned off. This sets the common mode voltage level Vcm of the differential signals presented to the receiver to the same level (Vtr) that the signals are transmitted by the transmitter.
Referring again to FIG. 2, in the AC coupled mode, the transmitted differential signals are coupled through AC coupling capacitors 7 to the receiver. At the front end interface device, the AC coupled mode is selected when the signals presented to the front end interface circuit have the values PWDN=0, ACMODE=0. This causes the transistors P12 and N12 to be turned on, and transistor P11 to be turned off. The common mode voltage (Vcm) of the differential signals is set to a value of between about 0.6 times and 0.8 times the power supply voltage Vdd (FIG. 4) by the resistive divider formed by resistors R1 and R2. However, some drawbacks of the front end interface circuit shown in FIG. 4 are that it does not perform DC offset cancellation, nor test for cable faults, nor provide for up-channel communication, such as is needed to transmit equalization information back to the transmitter for use in adjusting coefficients of a feed-forward equalizer at the transmitter.
Accordingly, it would be desirable to provide a receiver complex and method for receiving signals in which the aforementioned limitations of the prior art are addressed.